2018 Computer Architecture (ICT)

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Academic unit or major
Undergraduate major in Information and Communications Engineering
Sugino Nobuhiko  Isshiki Tsuyoshi 
Class Format
Media-enhanced courses
Day/Period(Room No.)
Tue3-4(W641)  Fri3-4(W641)  
Course number
Academic year
Offered quarter
Syllabus updated
Lecture notes updated
Language used
Access Index

Course description and aims

This lecture forcuses basic knowledge on various techniques exploited in high-performance processor architecutres.
This lecture forcuses basic knowledge on important techniques exploited in high-performance processor architecutres.
The lecture also provides recent high-performance processor technologies such as multi-processor architecture,
system-on-chip, and etc.

This course has two aims. The first is to teach students to understand important techniques exploited
in high-performance processor architecutres, such as pipeline, cache, memory management, and etc..
The other is to teach students to understand recent high-performance processor technologies
such as multi-processor architecture, system-on-chip, and etc.

Student learning outcomes

At the end of this course, students will be able to understand
- Fundamental techniques exploited in High-Performance processors (Pipeline, Cache, Memory Management)
- Multi-processor architectures
- Techniques utilized in "system-on-chip"


Pipeline, Cache, Virtual Memory, Multi-Processor, System-on-Chip

Competencies that will be developed

Specialist skills Intercultural skills Communication skills Critical thinking skills Practical and/or problem-solving skills

Class flow

1) At the beginning of each class, the previous class are reviewed.
2) Towards the end of class, students are given exercise problems related to what is taught on that day to solve.
3) Before coming to class, students should read the course schedule and check what topics will be covered. Required learning should be completed outside of the classroom for preparation and review purposes.

Course schedule/Required learning

  Course schedule Required learning
Class 1 Techniques exploited in high-performance processors and their evaluation schemes Learn history of high-performance processors and their evaluation schemes, and understand the aim of the lecture.
Class 2 Instruction set architecture Review contents in "ICT.I216 : Computer Logic Design (ICT)" and understand instruction set architecture.
Class 3 Pipeline 1 : Pipeline execution of instructions Understand pipeline execution of instructions.
Class 4 Pipeline 2 : Pipeline hazards and Understand pipeline hazards and their countermeasure methods.
Class 5 Pipeline 3 : Speculative execution Understand concepts of speculative execution and hardware expansion for its implementation.
Class 6 Memory 1 : Hierarchy of Memory and Cache Learn hierarchy of memory, and understand concepts of cache and its hardware.
Class 7 Memory 2 : Memory management scheme Understand concepts of virtual memory scheme and memory management hardware for its implementation.
Class 8 High-performance computation schemes Understand high-performance computation schemes such as SIMD, and etc.
Class 9 Inter-processor communication scheme Understand fundamental inter-processor communication schemes.
Class 10 Multi-processor 1 : Multi-processor architectures Understand various multi-processor architectures.
Class 11 Multi-processor 2 : Inter-core commuinication and synchronization techniques Understand inter-core communication and synchronization techniques in multi-processors
Class 12 Multi-processor architecture : Massively parallel processor Understand recent massively parallel processor architectures.
Class 13 System-on-chip 1 : Embedded processors Understand embedded processors, which have different properties from general purpose processors.
Class 14 System-on-chip 2 : Software design and development Understand software design and development for system-on-chip.
Class 15 System-on-chip : Practical system examples By practical system example, understand practical system-on-chip implementation.


Course materials are provided OCW-i.

Reference books, course materials, etc.

D. A. Patterson and J. L. Hennessy, "Computer Organization and Design 5th Edition," Elsevier Inc. (2014)

Assessment criteria and methods

1) Students will be assessed on their understanding of techniques in high performance processors, multi-processor architectures,
and system-on-chips.
2) Students’ course scores are based on examination (100%).
3) Full attendance is compulsory.
4) The instructor may fail a student if he/she repeatedly does not attend too often and/or comes to class late too often.

Related courses

  • ICT.I216 : Computer Logic Design (ICT)
  • ICT.I303 : Integrated Circuit Design
  • ICT.I415 : VLSI System Design
  • ICT.I501 : Engineering of System LSI Design (System Design)
  • ICT.I211 : Theory and Design of Logic Circuits
  • ICT.I317 : Embedded Systems
  • ICT.I516 : Engineering of System LSI Design (Embedded Software Design)

Prerequisites (i.e., required knowledge, skills, courses, etc.)

Students are strongly recommended to attand at the "ICT.I216 : Computer Logic Design (ICT)" class.

Contact information (e-mail and phone)    Notice : Please replace from "[at]" to "@"(half-width character).

Nobuhiko Sugino : sugino.n.aa[at]m.titech.ac.jp
Tsuyoshi Isshiki :

Office hours

Contact by e-mail in advance to schedule an appointment.

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