The objective of this course is to unify high-performance and low-energy design methodologies, techniques and algorithms that are essential for modern Nano-scale VLSI design. The course will focus the main design factors such as interconnects, clocking, arithmetic circuits and memories.
The outcome of this course is in an understanding and acquisition of analysis knowledge for designing modern digital VLSI circuits and systems. The student will be able to transform an “abstract” design goal into concrete hardware solution that meets given specification, and make the optimal tradeoff between the various design factors such as performance, power, area, cost and time-to-market.
CMOS, Interconnect, Signal propagation, Adders, Multipliers, Memories, Clocking, and Low-power design
Materials are taken for a variety of sources. Every lecture will point to relevant sources.
|第1回||CMOS overview||static, dynamic and pass-gate CMOS, back-of-the-envelope calculations, logic effort.|
|第2回||Interconnect design||capacitance, resistance, inductance, noise interference, repeaters, and process technology trends.|
|第3回||Signal propagation analysis||lumped and distributed models, closed form solutions, Elmore delay, and Penfield-Rubinstein algorithm.|
|第4回||Adders design||carry-lookahead adders, tree adders, multi-operand adders.|
|第5回||Multipliers design||parallel and sequential multipliers, high-radix multipliers, tree and array multiplication, pipelining, low-power implementations.|
|第6回||Memories design||SRAM, DRAM, eDRAM, new technologies.|
|第7回||Clocking||clock generation, PLL, DLL, clock distribution, clock gating.|
|第8回||Low-power design||signal encoding, power gating, dynamic voltage scaling.|
All lectures slides will be available on-line.
Learning achievement is evaluated by the quality of the written reports, exercise problems, and etc.
A basic knowledge of VLSI CMOS knowledge is assumed.
atsushi [at] ict.e.titech.ac.jp
Contact by e-mail in advance to schedule an appointment