This course aims to provide students with cutting-edge technologies and future trends of computer architecture with focusing on a microprocessor which plays an important role in the downsizing, personalization, and improvement of performance and power consumption of computer systems such as PCs, personal mobile devices, and embedded systems.
In this course, first, along with important concepts of computer architecture, students will learn from instruction set architectures to mechanisms for extracting instruction level parallelism used in out-of-order superscalar processors. After that, students will learn mechanisms for exploiting thread level parallelism adopted in multi-processors and multi-core processors.
By taking this course, students will learn:
(1) Basic principles for building today’s high-performance computer systems
(2) Mechanisms for extracting instruction level parallelism used in high-performance microprocessors
(3) Methods for exploiting thread level parallelism adopted in multi-processors and multi-core processors
(4) New inter-relationship between software and hardware
Computer Architecture, Processor, Embedded System, multi-processor, multi-core processor
|Intercultural skills||Communication skills||Specialist skills||Critical thinking skills||Practical and/or problem-solving skills|
Before coming to class, students should read the course schedule and check what topics will be covered. Required learning should be completed outside of the classroom for preparation and review purposes.
|Course schedule||Required learning|
|Class 1||Design and Analysis of Computer Systems||Understand the basic of design and analysis of computer systems.|
|Class 2||Instruction Set Architecture||Understand the examples of instruction set architectures|
|Class 3||Memory Hierarchy Design||Understand the organization of memory hierarchy designs|
|Class 4||Pipelining||Understand the idea and organization of pipelining|
|Class 5||Instruction Level Parallelism: Concepts and Challenges||Understand the idea and requirements for exploiting instruction level parallelism|
|Class 6||Instruction Level Parallelism: Instruction Fetch and Branch Prediction||Understand the organization of instruction fetch and branch predictions to exploit instruction level parallelism|
|Class 7||Instruction Level Parallelism: Advanced Techniques for Branch Prediction||Understand the advanced techniques for branch prediction to exploit instruction level parallelism|
|Class 8||Instruction Level Parallelism: Dynamic Scheduling||Understand the dynamic scheduling to exploit instruction level parallelism|
|Class 9||Instruction Level Parallelism: Exploiting ILP Using Multiple Issue and Speculation||Understand the multiple issue mechanism and speculation to exploit instruction level parallelism|
|Class 10||Instruction Level Parallelism: Out-of-order Execution and Multithreading||Understand the out-of-order execution and multithreading to exploit instruction level parallelism|
|Class 11||Multi-Processor: Distributed Memory and Shared Memory Architecture||Understand the distributed memory and shared memory architecture for multi-processors|
|Class 12||Thread Level Parallelism: Coherence and Synchronization||Understand the coherence and synchronization for thread level parallelism|
|Class 13||Thread Level Parallelism: Memory Consistency Model||Understand the memory consistency model for thread level parallelism|
|Class 14||Thread Level Parallelism: Interconnection Network||Understand the interconnection network for thread level parallelism|
|Class 15||Thread Level Parallelism: Many-core Processor and Network-on-chip||Understand the many-core processor and network-on-chip for thread level parallelism|
John L. Hennessy, David A. Patterson. Computer Architecture A Quantitative Approach, Fifth Edition. Morgan Kaufmann Publishers Inc., 2012
William James Dally, Brian Patrick Towles. Principles and Practices of Interconnection Networks. Morgan Kaufman Publishers Inc., 2004.
Students will be assessed on their understanding of instruction level parallelism, multi-processor, and thread level parallelism. Students’ course scores are based on the mid-term report (40%) and final report (60%).
No prerequisites are necessary, but enrollment in the related courses is desirable.
Kise Kenji: kise[at]cs.titech.ac.jp, 03-5734-3698
Miyazaki Jun: miyazaki[at]cs.titech.ac.jp, 03-5734-2687
Contact by e-mail in advance to schedule an appointment.