- 開講元
- 工学院
- 担当教員名
- WIMER SHMUEL
- 授業形態
- 講義
- メディア利用科目
- 曜日・時限(講義室)
- 木3-4(S322)
- クラス
- -
- 科目コード
- XEG.S605
- 単位数
- 1
- 開講年度
- 2019年度
- 開講クォーター
- 3Q
- シラバス更新日
- 2019年3月18日
- 講義資料更新日
- 2019年11月14日
- 使用言語
- 英語
- アクセスランキング
-
media
講義の概要とねらい
The objective of this course is to unify high-performance and low-energy design methodologies, techniques and algorithms that are essential for modern Nano-scale VLSI design. The course will focus the main design factors such as interconnects, clocking, arithmetic circuits and memories.
到達目標
The outcome of this course is in an understanding and acquisition of analysis knowledge for designing modern digital VLSI circuits and systems. The student will be able to transform an “abstract” design goal into concrete hardware solution that meets given specification, and make the optimal tradeoff between the various design factors such as performance, power, area, cost and time-to-market for future advanced VLSI design.
キーワード
CMOS, Interconnect, Signal propagation, Adders, Multipliers, Memories, Clocking, and Low-power design
学生が身につける力(ディグリー・ポリシー)
| ✔ 専門力 | 教養力 | コミュニケーション力 | ✔ 展開力(探究力又は設定力) | 展開力(実践力又は解決力) |
授業の進め方
Materials are taken for a variety of sources. Every lecture will point to relevant sources.
授業計画・課題
| 授業計画 | 課題 | |
|---|---|---|
| 第1回 | CMOS overview | static, dynamic and pass-gate CMOS, back-of-the-envelope calculations, logic effort. |
| 第2回 | Interconnect design | capacitance, resistance, inductance, noise interference, repeaters, and process technology trends. |
| 第3回 | Signal propagation analysis | lumped and distributed models, closed form solutions, Elmore delay, and Penfield-Rubinstein algorithm. |
| 第4回 | Adders design | carry-lookahead adders, tree adders, multi-operand adders. |
| 第5回 | Multipliers design | parallel and sequential multipliers, high-radix multipliers, tree and array multiplication, pipelining, low-power implementations. |
| 第6回 | Memories design | SRAM, DRAM, eDRAM, new technologies. |
| 第7回 | Clocking | clock generation, PLL, DLL, clock distribution, clock gating. |
| 第8回 | Low-power design | signal encoding, power gating, dynamic voltage scaling. |
教科書
None
参考書、講義資料等
All lectures slides will be available on-line.
成績評価の基準及び方法
Learning achievement is evaluated by the quality of the written reports, exercise problems, and etc.
関連する科目
- XEG.S404 ： グラフ理論とその応用
- XEG.S405 ： ディジタルVLSI設計
履修の条件(知識・技能・履修済科目等)
A basic knowledge of VLSI CMOS knowledge is assumed.
連絡先（メール、電話番号） ※”[at]”を”@”(半角)に変換してください。
atsushi [at] ict.e.titech.ac.jp
オフィスアワー
Contact by e-mail in advance to schedule an appointment
