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School of Engineering
- Undergraduate major in Mechanical Engineering
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- School of Materials and Chemical Technology
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- 工学院，物質理工学院，環境・社会理工学院共通科目
- Liberal arts and basic science courses
- First-Year Courses
- School of Science
- School of Engineering
- School of Materials and Chemical Technology
- School of Computing
- School of Life Science and Technology
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School of Environment and Society
- Department of Architecture and Building Engineering
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- Graduate major in Technology and Innovation Management
- Common courses
- Liberal arts and basic science courses
- Academic unit or major
- School of Engineering
- Instructor(s)
- Wimer Shmuel
- Class Format
- Lecture
- Media-enhanced courses
- Day/Period(Room No.)
- Thr3-4(S322)
- Group
- -
- Course number
- XEG.S405
- Credits
- 1
- Academic year
- 2019
- Offered quarter
- 3Q
- Syllabus updated
- 2019/3/18
- Lecture notes updated
- 2019/11/7
- Language used
- English
- Access Index
-
Course description and aims
The objective of this course is to unify high-performance and low-energy design methodologies, techniques and algorithms that are essential for modern Nano-scale VLSI design. The course will focus the main design factors such as interconnects, clocking, arithmetic circuits and memories.
Student learning outcomes
The outcome of this course is in an understanding and acquisition of analysis knowledge for designing modern digital VLSI circuits and systems. The student will be able to transform an “abstract” design goal into concrete hardware solution that meets given specification, and make the optimal tradeoff between the various design factors such as performance, power, area, cost and time-to-market.
Keywords
CMOS, Interconnect, Signal propagation, Adders, Multipliers, Memories, Clocking, and Low-power design
Competencies that will be developed
| ✔ Specialist skills | Intercultural skills | Communication skills | Critical thinking skills | Practical and/or problem-solving skills |
Class flow
Materials are taken for a variety of sources. Every lecture will point to relevant sources.
Course schedule/Required learning
| Course schedule | Required learning | |
|---|---|---|
| Class 1 | CMOS overview | static, dynamic and pass-gate CMOS, back-of-the-envelope calculations, logic effort. |
| Class 2 | Interconnect design | capacitance, resistance, inductance, noise interference, repeaters, and process technology trends. |
| Class 3 | Signal propagation analysis | lumped and distributed models, closed form solutions, Elmore delay, and Penfield-Rubinstein algorithm. |
| Class 4 | Adders design | carry-lookahead adders, tree adders, multi-operand adders. |
| Class 5 | Multipliers design | parallel and sequential multipliers, high-radix multipliers, tree and array multiplication, pipelining, low-power implementations. |
| Class 6 | Memories design | SRAM, DRAM, eDRAM, new technologies. |
| Class 7 | Clocking | clock generation, PLL, DLL, clock distribution, clock gating. |
| Class 8 | Low-power design | signal encoding, power gating, dynamic voltage scaling. |
Textbook(s)
None
Reference books, course materials, etc.
All lectures slides will be available on-line.
Assessment criteria and methods
Learning achievement is evaluated by the quality of the written reports, exercise problems, and etc.
Related courses
- XEG.S404 ： Graph Theory with Engineering Application
- XEG.S605 ： Advanced Topics in Digital VLSI Design
Prerequisites (i.e., required knowledge, skills, courses, etc.)
A basic knowledge of VLSI CMOS knowledge is assumed.
Contact information (e-mail and phone) Notice : Please replace from "[at]" to "@"(half-width character).
atsushi [at] ict.e.titech.ac.jp
Office hours
Contact by e-mail in advance to schedule an appointment
