2020 VLSI System Design

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Academic unit or major
Graduate major in Information and Communications Engineering
Isshiki Tsuyoshi 
Course component(s)
Lecture    (ZOOM)
Day/Period(Room No.)
Tue5-6(Zoom)  Fri5-6(Zoom)  
Course number
Academic year
Offered quarter
Syllabus updated
Lecture notes updated
Language used
Access Index

Course description and aims

This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.

Student learning outcomes

Develop deep understanding of mathematical theories and algorithms for solving important CAD problems for VLSI system designs, especially in logic synthesis and high-level synthesis.


VLSI, system design, logic synthesis, high-level synthesis, optimization problems

Competencies that will be developed

Specialist skills Intercultural skills Communication skills Critical thinking skills Practical and/or problem-solving skills

Class flow

Various optimization problems and the corresponding algorithms will be explained, and assignments on the related problems will be given.

Course schedule/Required learning

  Course schedule Required learning
Class 1 Introduction - VLSI design methodology and computer-aided design (CAD) tools Understand the VLSI design methodology and the role of CAD tools
Class 2 Introduction - Hardware description language and hardware behavior model Understand Hardware Description Language
Class 3 Logic synthesis - Conversion from RTL description to logic equations Understand the relationship between RTL description and logic function
Class 4 Logic synthesis - Two-level logic minimization Understand two-level logic minimization methods and related theories
Class 5 Logic synthesis - Multi-level logic minimization Understand multi-level logic minimization methods and related theories
Class 6 Logic synthesis - Area-optimal technology mapping Understand technology mapping methods and related dynamic programming techniques
Class 7 Logic synthesis - Delay-optimal technology mapping Understand delay-optimal technology mapping methods
Class 8 Logic synthesis - Fan-out optimization Understand fan-out optimization techniques and overall technology mapping flow
Class 9 Cell libraries and datapath libraries Understand design methodologies for cell libraries
Class 10 High-level synthesis - Design methodology Understand the design methodology using high-level synthesis
Class 11 High-level synthesis - Operation scheduling Understand operation scheduling methods
Class 12 High-level synthesis - Resource allocation Understand resource allocation methods and related optimization techiques
Class 13 Advanced topics in system-level design issues (1) Understand latest research activities in system-level design issues
Class 14 Advanced topics in system-level design issues (2) Understand latest research activities in system-level design issues

Out-of-Class Study Time (Preparation and Review)

To enhance effective learning, students are encouraged to spend approximately 100 minutes preparing for class and another 100 minutes reviewing class content afterwards (including assignments) for each class.
They should do so by referring to textbooks and other course material.


Not determined

Reference books, course materials, etc.

Lecture materials will be distributed

Assessment criteria and methods

Grades based on assignment reports

Related courses

  • ICT.I211 : Theory and Design of Logic Circuits
  • ICT.I216 : Computer Logic Design (ICT)

Prerequisites (i.e., required knowledge, skills, courses, etc.)

Knowledge on logic circuit is desired

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