2019 VLSI System Design

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Academic unit or major
Graduate major in Information and Communications Engineering
Instructor(s)
Isshiki Tsuyoshi 
Course component(s)
Lecture
Day/Period(Room No.)
Tue5-6(S622)  Fri5-6(S622)  
Group
-
Course number
ICT.I415
Credits
2
Academic year
2019
Offered quarter
3Q
Syllabus updated
2019/4/19
Lecture notes updated
2019/11/15
Language used
English
Access Index

Lecture

Lecture 1 Introduction - VLSI design methodology and computer-aided design (CAD) tools

2019.9.27(Fri.) 5-6Session

Lecture

Lecture 2 Introduction - Hardware description language and hardware behavior model

2019.10.1(Tue.) 5-6Session

Lecture

Lecture 3 Logic synthesis - Conversion from RTL description to logic equations

Lecture

Lecture 4 Logic synthesis - Two-level logic minimization

2019.10.8(Tue.) 5-6Session

Lecture

Lecture 5 Logic synthesis - Multi-level logic minimization

Lecture

Lecture 6 Logic synthesis - Area-optimal technology mapping

2019.10.15(Tue.) 5-6Session

Lecture

Lecture 7 Logic synthesis - Delay-optimal technology mapping

2019.10.18(Fri.) 5-6Session

Lecture

Lecture 8 Logic synthesis - Fan-out optimization

Lecture

Lecture 9 Cell libraries and datapath libraries

2019.10.29(Tue.) 5-6Session

Lecture

Lecture 10 High-level synthesis - Design methodology

2019.11.1(Fri.) 5-6Session

Lecture

Lecture 11 High-level synthesis - Operation scheduling

2019.11.5(Tue.) 5-6Session

Lecture

Lecture 12 High-level synthesis - Resource allocation

Lecture

Lecture 13 Advanced topics in system-level design issues (1)

2019.11.12(Tue.) 5-6Session

Lecture

Lecture 14 Advanced topics in system-level design issues (2)

2019.11.15(Fri.) 5-6Session

Lecture

Lecture 15 Advanced topics in system-level design issues (3)

2019.11.19(Tue.) 5-6Session

Lecture

Lecture 16  

2019.11.22(Fri.) 5-6Session

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