2018 | VLSI System Design - TOKYO TECH OCW

2018　VLSI System Design

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Academic unit or major: Graduate major in Information and Communications Engineering

Instructor(s): Isshiki Tsuyoshi

Class Format: Lecture

Media-enhanced courses

Day/Period(Room No.): Tue5-6(S622) Fri5-6(S622)

Group: -

Course number: ICT.I415

Credits: 2

Academic year: 2018

Offered quarter: 3Q

Syllabus updated: 2018/11/30

Lecture notes updated: 2018/9/28

Language used: English

Access Index

Course description and aims

This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.

Student learning outcomes

Develop deep understanding of mathematical theories and algorithms for solving important CAD problems for VLSI system designs, especially in logic synthesis and high-level synthesis.

Keywords

VLSI, system design, logic synthesis, high-level synthesis, optimization problems

Competencies that will be developed

✔ Specialist skills

Intercultural skills

Communication skills

✔ Critical thinking skills

✔ Practical and/or problem-solving skills

Class flow

Various optimization problems and the corresponding algorithms will be explained, and assignments on the related problems will be given.

Course schedule/Required learning

	Course schedule	Required learning
Class 1	Introduction - VLSI design methodology and computer-aided design (CAD) tools	Understand the VLSI design methodology and the role of CAD tools
Class 2	Introduction - Hardware description language and hardware behavior model	Understand Hardware Description Language
Class 3	Logic synthesis - Conversion from RTL description to logic equations	Understand the relationship between RTL description and logic function
Class 4	Logic synthesis - Two-level logic minimization	Understand two-level logic minimization methods and related theories
Class 5	Logic synthesis - Multi-level logic minimization	Understand multi-level logic minimization methods and related theories
Class 6	Logic synthesis - Area-optimal technology mapping	Understand technology mapping methods and related dynamic programming techniques
Class 7	Logic synthesis - Delay-optimal technology mapping
Class 8	Logic synthesis - Fan-out optimization
Class 9	Cell libraries and datapath libraries	Understand design methodologies for cell libraries
Class 10	High-level synthesis - Design methodology	Understand the design methodology using high-level synthesis
Class 11	High-level synthesis - Operation scheduling	Understand operation scheduling methods
Class 12	High-level synthesis - Resource allocation	Understand resource allocation methods and related optimization techiques
Class 13	Advanced topics in system-level design issues (1)	Understand latest research activities in system-level design issues
Class 14	Advanced topics in system-level design issues (2)
Class 15	Advanced topics in system-level design issues (3)

Textbook(s)

Not determined

Reference books, course materials, etc.

Lecture materials will be distributed

Assessment criteria and methods

Grades based on assignment reports

Related courses

ICT.I211 ： Theory and Design of Logic Circuits
ICT.I216 ： Computer Logic Design (ICT)

Prerequisites (i.e., required knowledge, skills, courses, etc.)

Knowledge on logic circuit is desired

TOKYO INSTITUTE OF TECHNOLOGY