Exercises on microprocessor software(instruction set, assembly programming) and hardware(arithmetic logic, control logic) designs and FPGA board operation is given from the lab textbook. In the second half of the lab class, groups of 2 to 3 persons will choose a free topic on microprocessor design enhancement, and the group will work together from planning, implementation and documentation to experience the group work.
Obtain skills to program a 16-bit microprocessor using assembly language.
Obtain skills to design and simulate a microprocessor using hardware description language.
Obtain skills to verify microprocessor behavior on FPGA board.
Experience the group work on microprocessor design enhancement project including planning, specification design, implementation, design verification, design evaluation and documentation of the whole process.
Microprocessor, instruction set, assembly programming, hardware description language, FPGA
✔ Specialist skills | Intercultural skills | ✔ Communication skills | ✔ Critical thinking skills | ✔ Practical and/or problem-solving skills |
Groups of 2 to 3 persons will conduct assembly programming, Verilog simulation, FPGA verification, and free topic project, and submit report on each subject.
Course schedule | Required learning | |
---|---|---|
Class 1 | Assembly programming exercise 1: Instruction set, instruction format, assembly language format | Instruction set, instruction format, assembly language format |
Class 2 | Assembly programming exercise 2: multiplication programming, division programming | multiplication programming, division programming |
Class 3 | Assembly programming exercise 3: prime number calculation | prime number calculation |
Class 4 | Assembly programming exercise 4: program analysis (calculator program, IO program) | program analysis (calculator program, IO program) |
Class 5 | Hardware description language exercise 1: Verilog language format | Verilog language format |
Class 6 | Hardware description language exercise 2: block diagram extractions from Verilog hierarchical descriptions | block diagram extractions from Verilog hierarchical descriptions |
Class 7 | Hardware description language exercise 3: instruction execution flow graph extractions from Verilog instruction execution descriptions | instruction execution flow graph extractions from Verilog instruction execution descriptions |
Class 8 | Hardware description language exercise 4: Verilog simulations of microprocessor program executions | Verilog simulations of microprocessor program executions |
Class 9 | FPGA board microprocessor exercise 1: microprocessor implementation on FPGA board and behavior verification of program executions | microprocessor implementation on FPGA board and behavior verification of program executions |
Class 10 | FPGA board microprocessor exercise 2: microprocessor communication verifications using multiple FPGA boards | microprocessor communication verifications using multiple FPGA boards |
Class 11 | Advanced microprocessor design exercise 1: Planning of microprocessor design enhancement (instruction set extensions, software design, etc) | Planning of microprocessor design enhancement (instruction set extensions, software design, etc) |
Class 12 | Advanced microprocessor design exercise 2: specification design of enhanced microprocessor | specification design of enhanced microprocessor |
Class 13 | Advanced microprocessor design exercise 3: implementation of enhanced microprocessor | implementation of enhanced microprocessor |
Class 14 | Advanced microprocessor design exercise 4: design verification of enhanced microprocessor | design verification of enhanced microprocessor |
Class 15 | Advanced microprocessor design exercise 5: design evaluation and documentations of enhanced microprocessor | design evaluation and documentations of enhanced microprocessor |
Lab textbook will be distributed on the lab's web page
Lab textbook will be distributed on the lab's web page
Grades are scored on the submitted reports
Advised to be enrolled in Switching Circuit Theory and Computer Logic Design classes
Appointments should be made via email