understand the basis of IC logic circuits, especially about the structure and characterization (circuit behavior and switching behavior) of digital integrated circuits, and learn that the integrated circuits are built through the logic circuits integration and layout design technologies.
Students will be able to understand principles and characteristics of MOS transistor and learn the structure of CMOS logic circuits, design methods of layout and test generation for VLSI circuits.
Digital integrated circuit, logic, layout, MOS transistor
|Intercultural skills||Communication skills||Specialist skills||Critical thinking skills||Practical and/or problem-solving skills|
The overview of design flow for VLSI circuit design is first given, followed by explanation of principles and characteristics of MOS transistor. Then, the structures of CMOS logic circuits, register, and memory as a basic component of VLSI circuits are shown as well as a variety of design, verification, and test methods. Finally, a set of CAD tool environments and challenging issues induced by CMOS scaling are described.
|Course schedule||Required learning|
|Class 1||Design flow of VLSI circuit||learn the entire design flow of VLSI circuit|
|Class 2||MOS process and transistor||learn MOS process and transistor as basic components of digital logic circuit|
|Class 3||Behavior of MOS transistor||learn behaviors and conditions of MOS transistor|
|Class 4||CMOS inverter (DC characteristic, switching characteristic, and power consumption)||learn characteristics of CMOS inverter built based on MOS transistors|
|Class 5||Static logic circuit||learn fundamental behaviors of static logic circuit|
|Class 6||Dynamic logic circuit||learn fundamental behaviors of dynamic logic circuit|
|Class 7||Register and memory||learn structure and fundamental behaviors of register and memory|
|Class 8||IC logic design 1 (PLA)||learn design of IC logic circuit using PLA|
|Class 9||IC logic design 2 (standard cell and gate array)||learn design of IC logic circuit using standard cell and gate array|
|Class 10||IC layout 1 (design rule and mask layer)||learn design rules and mask layers needed for IC layout|
|Class 11||IC layout 2 (automatic place and route)||learn automation technologies of place and route for IC layout|
|Class 12||VLSI test 1 (error diagnosis)||learn error diagnosis technologies of VLSI|
|Class 13||VLSI test 2 (scan chain and test vector generation)||learn scan chain and test vector generation for VLSI test|
|Class 14||CAD tool environment (logic synthesis, layout, cell generation, and memory generation)||learn VLSI design automation (CAD) environments|
|Class 15||Design issues of CMOS scaling (process variation, power consumption, design efficiency)||learn a variety of design issues induced by CMOS scaling|
Integrated Circuit Design, Hiroaki Kunieda, 1996
Introduction to VLSI Systems，C. Mead and L. Conway， Addison-Wesley Publishing Company, 1980
Learning achievement (understanding and skill acquirement on the goals of this lecture) is evaluated by the final exam.