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2017　Fundamentals of Semiconductor Fabrication Process

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Academic unit or major
Graduate major in Electrical and Electronic Engineering
Instructor(s)
Miyamoto Yasuyuki 
Class Format
Lecture     
Media-enhanced courses
Day/Period(Room No.)
Wed1-2(S223)  
Group
-
Course number
EEE.F491
Credits
1
Academic year
2017
Offered quarter
4Q
Syllabus updated
2017/3/22
Lecture notes updated
2018/1/10
Language used
Japanese
Access Index

Course description and aims

The instructor in this course will demonstrate the principles and limitations of the processing techniques for fabricating micro devices for making possible the increase in the speed of semiconductor devices.
The aim of this course is for students to understand that scaling of both lateral and vertical axes are essential in miniaturization, then to learn about the overview of the latest techniques, focusing on lithography.
Further, students will learn about the formation of doped layers, etching and the oxidization process, deposition, electrodes, and wiring.
The goal is for students to become capable of planning a rough process based on the course content described above.

Student learning outcomes

By the end of this course, students will be able to understand the principles of miniaturization of the semiconductor process based on the relationship between miniaturization and electronic devices and to prepare rough plans for its application.
Semiconductor processes requiring the understanding of principles of miniaturization include photolithography, RET, double patterning, electron beam lithography, resists, EUV, NGL, impurity diffusion, ion implantation, etching, oxidization process, high-κ dielectrics, contact resistance, TLM, wiring, SOI, and TSV.

Keywords

lithography, diffusion of impurity, ion implantation, etching, oxidation,
electrode, wiring

Competencies that will be developed

✔ Specialist skills Intercultural skills Communication skills Critical thinking skills Practical and/or problem-solving skills

Class flow

Due to the volume of material, simple calculations will be given as homework for each class. The final exam will be an open-book written exam. Reports will be assigned for planning processes.

Course schedule/Required learning

  Course schedule Required learning
Class 1 Requirements of directions of miniaturization of devices and basic of optical lithography Understanding relation between diffraction image and process dependent constant k1
Class 2 Present status of optical lithography with resist Calculation of image by using alternative phase shift mask
Class 3 Electron beam lithography with resist Simple calculation of proximity effect
Class 4 NGL and formation of doped layer Calculation of SRIM
Class 5 Etching and oxidation Calculation of thickness of oxidation layer from thermal condition
Class 6 Thin-film formation Evaluation of deposition condition by stagnant layer change in CVD
Class 7 Electrode and wiring Evaluation of electrode by TLM

Textbook(s)

N/A

Reference books, course materials, etc.

By OCW-i

Assessment criteria and methods

To be evaluated 35 % on homework, 30 % on exams and 30 % on reports

Related courses

  • EEE.D351 ： Electron Devices I
  • EEE.D352 ： Electron Devices II

Prerequisites (i.e., required knowledge, skills, courses, etc.)

Not required

Contact information (e-mail and phone)    Notice : Please replace from "[at]" to "@"(half-width character).

miya[at]ee.e.titech.ac.jp 03-5734-2572

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