2021 Semiconductor Fabrication Process

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Academic unit or major
Undergraduate major in Electrical and Electronic Engineering
Ohmi Shun-Ichiro 
Class Format
Media-enhanced courses
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Offered quarter
Syllabus updated
Lecture notes updated
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Course description and aims

Principles and limitations of micro-fabrication process in semiconductor devices for high-speed operation and high-density integration are described. After explanation of requirement of simultaneous miniaturization in vertical direction and lateral direction for high speed operations, latest technology with focusing on lithography are explained. Then, diffusion region, etching, oxidation, film deposition, and metallization are described.

Student learning outcomes

By the end of this course, students will be able to:
1) Explain outlines of semiconductor processes which fabricated integrated circuit for popularization of low-cost and high-speed electric circuits.
2) Understand the guidelines for higher integration and speed.
3) Understand the method for miniaturization based on the scaling from principle operation of MOSFETs.


Integrated circuits, CMOS, memory, lithography, diffusion region, etching, oxidation, film deposition, metallization

Competencies that will be developed

Specialist skills Intercultural skills Communication skills Critical thinking skills Practical and/or problem-solving skills
・Applied specialist skills on EEE

Class flow

Because of the large amount of knowledge, basic problems will be explained during the lecture. Any textbook or notebook is able to be used for the examination.

Course schedule/Required learning

  Course schedule Required learning
Class 1 Requirements of semiconductor fabrication process and basis of optical lithography Calculation of resolution for lithography process
Class 2 Advanced optical lithography and electron beam lithography Evaluation of resolution and proximity correction in lithography
Class 3 Short channel effect and scaling for MOSFET Explanation of self-aligned process
Class 4 Scaling of gate insulator and source/drain diffusion regions Extraction of SiO2 thickness and contact resistivity
Class 5 Scaling and technology booster Explanation of strained-channel, high-k gate insulator, and SOI substrate
Class 6 Advanced memory and integration process Calculation of wiring delay
Class 7 Examination

Out-of-Class Study Time (Preparation and Review)

To enhance effective learning, students are encouraged to spend approximately 100 minutes preparing for class and another 100 minutes reviewing class content afterwards (including assignments) for each class.
They should do so by referring to textbooks and other course material.



Reference books, course materials, etc.

Distributed by OCW-i

Assessment criteria and methods

Evaluate based on the students' knowledge of semiconductor processes.
Report 30%, Examination 70%

Related courses

  • EEE.D351 : Electron Devices I
  • EEE.D352 : Electron Devices II

Prerequisites (i.e., required knowledge, skills, courses, etc.)


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