2018 Digital Electronic Circuits

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Academic unit or major
Undergraduate major in Electrical and Electronic Engineering
Instructor(s)
Manaka Takaaki  Tabaru Marie 
Course component(s)
Lecture
Day/Period(Room No.)
Mon3-4(S222)  Thr3-4(S222)  
Group
-
Course number
EEE.C321
Credits
2
Academic year
2018
Offered quarter
1Q
Syllabus updated
2018/5/30
Lecture notes updated
-
Language used
Japanese
Access Index

Course description and aims

This course focuses on the fundamentals of digital circuit. Topics include binary number, logical algebra and its calculation, basic logic gate, combinational logic circuit, sequential circuit, arithmetic circuit and synchronous logic circuit. Most of electronic devices consists of digital circuit technique. By combining lectures and exercises, the course enables students to understand and acquire the fundamentals of logic circuit so that students can design a simple circuit. Students will experience the satisfaction of solving practical circuit problems by using their knowledge regarding a logic circuit acquired through this course.

Student learning outcomes

By the end of this course, students will be able to:
1) Understand and explain the fundamentals of logical algebra and logic gates.
2) Analyze and design a simple combinational logic circuit.
3) Analyze and design a simple sequential logic circuit.
4) Analyze and design a simple arithmetic logic circuit.
5) Explain memory and bus arrangement.

Keywords

Digital circuit, logic circuit, logical algebra, combinational logic circuit, flip-flop, sequential circuit, operational circuit

Competencies that will be developed

Intercultural skills Communication skills Specialist skills Critical thinking skills Practical and/or problem-solving skills
- - - -

Class flow

At the beginning of each class, solutions to exercise problems that were given at the previous class are reviewed. Towards the end of class, students are given exercise problems related to the lecture given that day to solve. To prepare for class, students should read the course schedule section and check what topics will be covered. Required learning should be completed outside of the classroom for preparation and review purposes. In the first half lectures we will take interactive exercises using Handbook.

Course schedule/Required learning

  Course schedule Required learning
Class 1 Digital information Understand binary operation, BCD code, and digital and analog
Class 2 Basic logic gate, Logical algebra Understand basic logic gate, Boolean algebra, De Morgan's law and simplification of equation
Class 3 Fundamentals of logic circuit Understand conversion between sum of products form and sum‐product form, half adder, full adder etc.
Class 4 Simplification of logic circuits 1 Understand combinational logic circuit, Karnaugh map with and without don't care.
Class 5 Simplification of logic circuits 2 Understand Quine–McCluskey algorithm
Class 6 CMOS logic gate Understand electrical properties of digital ICs and CMOS process
Class 7 Overall exercise of the first half of the course Review the first half of the course with exercise problems
Class 8 Test the level of understanding of the first half of the course Test level of understanding and evaluate achievement for classes 1–6.
Class 9 Flip-flop 1 Understand RS-FF, JK-FF and synchronous and asynchronous circuit
Class 10 Flip-flop 2 Understand Master-Slave FF, edge-trigger circuit, D-FF
Class 11 Application of Flip-flop Understand Shift-register and counter circuit
Class 12 Sequential circuit 1 Understand State transition diagram and table, and design the sequential circuit using various FFs
Class 13 Sequential circuit 2 Simplification of the sequential circuit and design N-ary counter
Class 14 Operation circuit, memory and bus arrangement Understand multiplying and dividing circuit, ALU, memory circuit and various buses
Class 15 Overall exercise of the latter half of the course Review the latter half of the course with exercise problems

Textbook(s)

並木秀明 「デジタル回路とVerilog HDL」技術評論社

Reference books, course materials, etc.

None

Assessment criteria and methods

Midterm exam (50%), final exam (50%)

Related courses

  • EEE.C331 : Computer Architecture (Electrical and Electronic Engineering)

Prerequisites (i.e., required knowledge, skills, courses, etc.)

None

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