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- Academic unit or major
- Computer Science
- Instructor(s)
- Miyazaki Jun Kise Kenji
- Class Format
- Lecture
- Media-enhanced courses
- Day/Period(Room No.)
- Mon1-2(W323) Thr1-2(W323)
- Group
- -
- Course number
- ZUS.P303
- Credits
- 2
- Academic year
- 2017
- Offered quarter
- 3Q
- Syllabus updated
- 2017/3/17
- Lecture notes updated
- -
- Language used
- Japanese
- Access Index
-
Course description and aims
This course focuses on how to organize and control modern high performance processors which are adopted into recent computer systems, and covers the concepts and techniques of the advanced computer architecture, such as pipeline processors, vector computers, parallel computers, interconnection networks, multicore processors, etc.
The concept of parallel processing by pipelining and multiprocessors is essential for fast computation, and becomes the basis of designing modern high performance processors. This course introduces not only hardware technologies but also the aspect of the corresponding software, i.e., programming models. Students will have the technologies of modern computer architecture from both aspects.
Student learning outcomes
At the end of this course, students will:
- Understand the concepts, principles, and properties of pipeline processors and superscalar processors from the aspects of both hardware and software,
- Understand the principles of vector processors and the relationship between their organization and performance,
- Understand the classification and organization of multiprocessor systems, and
- Understand the mechanisms of maintaining the consistency of data on multiprocessor systems from the aspects of both hardware and software.
Keywords
RISC, pipelining, vector computer, interconnection network, shared memory multiprocessor, message-passing multiprocessor, multicore processor
Competencies that will be developed
| ✔ Specialist skills | Intercultural skills | Communication skills | Critical thinking skills | Practical and/or problem-solving skills |
Class flow
In the first 80% of each class, the details of topics are described. The remainder will be spent for quizzes and their explanation to help students’ comprehension.
Course schedule/Required learning
| Course schedule | Required learning | |
|---|---|---|
| Class 1 | High performance processor and its evaluation | Explain the relationship between throughput and response time. Undersntad Amdahl's law. |
| Class 2 | Instruction set architecture / addressing mode / CISC | Explain the advantages and disadvantages of CISC processors. |
| Class 3 | RICS / piplining | Explain the advantages and disadvantages of RISC processors. Understand the principles of pipelining. |
| Class 4 | Hazard / static multiple issue processor / VLIW | Understand the hazard problems and explain their solutions. |
| Class 5 | Dyamic multiple issue processor / superscalar processor / Tomasulo's algorithm | Understand Tomasulo's algorithm |
| Class 6 | Arithmetic pipeline / non-linear pipelining | Explain the scheduling of non-linear pipelining. |
| Class 7 | Vector computer architecture | Explain the principles of vector computer architecture. |
| Class 8 | Advances and evaluations of vector computers | Understand how to estimate the performance of vector computers. |
| Class 9 | Static interconnection network / packet switching | Explain the variations of static interconnection networks and their routing methods. |
| Class 10 | Dynamic interconnection network | Explain how to organize dynamic interconnection networks. |
| Class 11 | Multiprocessor / shared memory multiprocessor / cache coherency / snooping cache coherence protocol | Explain snooping cache coherence protocol. |
| Class 12 | Directory-based cache coherence protocol / programiming model for shared memory multiprocessor | Understand thre relationship between cache coherence protocols and mutual exclusion among threads. |
| Class 13 | Distributed memory multiprocessor / message-passing / programming model for distributed memory multiprocessor | Understand the programming models for distributed memory multiprocessors. |
| Class 14 | Multicore processor / manycore processor / GPU | Undersntad the properties of multicore and manycore processors |
| Class 15 | Hardware multithreading / SIMD instructions / advanced topics | Undersntad hardware multithreading and SIMD instructions. |
Textbook(s)
None required.
Reference books, course materials, etc.
Handouts used in class can be found on OCW-i.
[Reference books]
- David A. Patterson, John L. Hennessy, “Computer Organization and Design -- The Hardware/Software Interface 5th Ed.”, Morgan Kaufmann, 2013
- John L. Hennessy, David A. Patterson, “Computer Architecture – A Quantitative Approach 5th Ed.”, Morgan Kaufmann, 2011
Assessment criteria and methods
The course scores are based on the term-end exam.
Related courses
- CSC.T341 ： Computer Logic Design
- ZUS.P302 ： Computer Architecture I
- CSC.T262 ： Assembly Language
- CSC.T376 ： Advances in Computer Science
Prerequisites (i.e., required knowledge, skills, courses, etc.)
No prerequisites are necessary, but enrollment in Computer Architecture I and Assembly Language is desirable.
