Prerequisite: VLSI design methodology or equivalent
Representation of Boolean function. Synthesis of two-level and multi-level combinational circuits. Synthesis of sequential circuits. Test and synthesis for test ability. Decomposition, allocation, assignment and scheduling in high-level synthesis.
This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.
1.Introduction - VLSI design methodology and computer-aided design (CAD) tools
2.Introduction - Hardware description language and hardware behavior model
3.Logic synthesis - Two-level logic minimization
4.Logic synthesis - Multi-level logic minimization
5.Logic synthesis - Area-optimal technology mapping
6.Logic synthesis - Delay-optimal technology mapping
7.Logic synthesis - Fan-out optimization
8.High-level synthesis - Design methodology
9.High-level synthesis - Operation scheduling
10.High-level synthesis - Resource allocation
11.Advanced topics in system-level design issues
Lecture notes can be downloaded from the WEB.
Recommended textbooks :
・Sabih H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 1999
・Srinivas Devadas, et al., "Logic Synthesis", McGraw-Hill, 1994
・Jan Vanhoof, et al., "High-Level Synthesis for Real-Time Digital
・Signal Processing", Kluwer Academic Publishers, 1992
"Introduction to Algorithms"(離散構造とアルゴリズム) and "Integrated Circuit Design"(集積回路設計) are prerequisite.
Grades based on reports
Students interested in any aspects of VLSI design are welcomed.