VLSI Design Methodologies

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Kunieda Hiroaki 
Lecture2  Exercise0  Experiment0
Syllabus updated
Lecture notes updated
Spring Semester

Outline of lecture

The design flow of Standard Cell Design for VLSI is discussed, which includes RTL design, Logic design, Logic verification, Layout design and Layout verification. In addition to that, FPGA design and System level Soc design will also be described.

Purpose of lecture

According to the design flow of Standard Cell Design, the hierarchical design and verification based on standard cell design will be discussed including hardware description language, logic design and layout design and their verifications.

Plan of lecture

シ托シ桟LSI Overview
シ抵シ桟lSI_Basic I
シ難シ桟lSI_Basic II
シ費シ惨tandard Cell Design_Overview
シ包シ惨tandard Cell Design_RTL
シ厄シ惨tandard Cell Design_Logic I
シ暦シ惨tandard Cell Design_LogicII
シ假シ惨tandard Cell Design_Verify
シ呻シ惨tandard Cell Design_Layout
10シ惨tandard Cell Design_Layout Verification
11シ薩PGA Design
12シ惨ystem on Chip (SoC) Design

Textbook and reference

Wayne Wolf: Modern VLSI Design (System on Silicon) Second Edition, Prentice Hall 1998.

Related and/or prerequisite courses

VLSI Layout Design, VLSI System Design are related subjects.



Comments from lecturer

VLSI design is the basic knowledge for engineers of various fields. This lecture covers all aspects of VLSI design, especially for the beginners of VLSI design.

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