VLSI System Design

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Isshiki Tsuyoshi 
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Syllabus updated
Lecture notes updated
Fall Semester

Outline of lecture


Prerequisite: VLSI design methodology or equivalent Representation of Boolean function. Synthesis of two-level and multi-level combinational circuits. Synthesis of sequential circuits. Test and synthesis for test ability. Decomposition, allocation, assignment and scheduling in high-level synthesis.

Purpose of lecture

This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.

Plan of lecture

01.Introduction - VLSI design methodology and computer-aided design (CAD) tools
02.Introduction - Hardware description language and hardware behavior model
03.Logic synthesis - Two-level logic minimization
04.Logic synthesis - Multi-level logic minimization
05.Logic synthesis - Area-optimal technology mapping
06.Logic synthesis - Delay-optimal technology mapping
07.Logic synthesis - Fan-out optimization
08.High-level synthesis - Design methodology
09.High-level synthesis - Operation scheduling
10.High-level synthesis - Resource allocation
11.Advanced topics in system-level design issues

Textbook and reference

Lecture notes can be downloaded from the WEB.
Recommended textbooks :

繝サSabih H. Gerez, ""Algorithms for VLSI Design Automation"", John Wiley & Sons, 1999
繝サSrinivas Devadas, et al., ""Logic Synthesis"", McGraw-Hill, 1994
繝サJan Vanhoof, et al., ""High-Level Synthesis for Real-Time Digital
繝サSignal Processing"", Kluwer Academic Publishers, 1992

Related and/or prerequisite courses

Introduction to Algorithmsシ磯屬謨」讒矩縺ィ繧「繝ォ繧エ繝ェ繧コ繝シ and ""Integrated Circuit Design""シ磯寔遨榊屓霍ッ險ュ險茨シ are prerequisite.


Grades based on reports

Comments from lecturer

Students interested in any aspects of VLSI design are welcomed.

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