- Lecturer
- Isshiki Tsuyoshi
- Place
- Tue5-6(S321)
- Credits
- Lecture2 Exercise0 Experiment0
- Code
- 56011
- Syllabus updated
- 2010/9/20
- Lecture notes updated
- 2010/9/20
- Semester
- Fall Semester
Outline of lecture
VLSI繧ｷ繧ｹ繝繝CAD縺ｫ縺翫¢繧玖ｫ也炊蜷域撰ｼ後ユ繧ｹ繝茨ｼ後い繝ｼ繧ｭ繝繧ｯ繝√Ε蜷域千ｭ峨ｮ隕∫ｴ謚陦薙→險ｭ險郁ｪ蜍募喧縺ｮ迴ｾ迥ｶ繝ｻ蝠城｡檎せ縺ｫ縺､縺縺ｦ隰幄ｿｰ縺吶ｋ縲ゆｸｻ縺ｪ蜀螳ｹ縺ｯｼ鯉ｼ呈ｮｵ隲也炊繝ｻ螟壽ｮｵ隲也炊蜷域撰ｼ碁蠎丞屓霍ｯ蜷域撰ｼ後ユ繧ｹ繝育函謌撰ｼ後い繝ｼ繧ｭ繝繧ｯ繝√Ε蜷域舌↑縺ｩ縺ｧ縺ゅｋ縲
Prerequisite: VLSI design methodology or equivalent Representation of Boolean function. Synthesis of two-level and multi-level combinational circuits. Synthesis of sequential circuits. Test and synthesis for test ability. Decomposition, allocation, assignment and scheduling in high-level synthesis.
Purpose of lecture
This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.
Plan of lecture
01.Introduction - VLSI design methodology and computer-aided design (CAD) tools
02.Introduction - Hardware description language and hardware behavior model
03.Logic synthesis - Two-level logic minimization
04.Logic synthesis - Multi-level logic minimization
05.Logic synthesis - Area-optimal technology mapping
06.Logic synthesis - Delay-optimal technology mapping
07.Logic synthesis - Fan-out optimization
08.High-level synthesis - Design methodology
09.High-level synthesis - Operation scheduling
10.High-level synthesis - Resource allocation
11.Advanced topics in system-level design issues
Textbook and reference
Lecture notes can be downloaded from the WEB.
Recommended textbooks :
繝ｻSabih H. Gerez, ""Algorithms for VLSI Design Automation"", John Wiley & Sons, 1999
繝ｻSrinivas Devadas, et al., ""Logic Synthesis"", McGraw-Hill, 1994
繝ｻJan Vanhoof, et al., ""High-Level Synthesis for Real-Time Digital
繝ｻSignal Processing"", Kluwer Academic Publishers, 1992
Related and/or prerequisite courses
Introduction to Algorithmsｼ磯屬謨｣讒矩縺ｨ繧｢繝ｫ繧ｴ繝ｪ繧ｺ繝ｼ and ""Integrated Circuit Design""ｼ磯寔遨榊屓霍ｯ險ｭ險茨ｼ are prerequisite.
Evaluation
Grades based on reports
Comments from lecturer
Students interested in any aspects of VLSI design are welcomed.
