- Lecturer
- Isshiki Tsuyoshi
- Place
- Tue5-6(S321)
- Credits
- Lecture2 Exercise0 Experiment0
- Code
- 56011
- Syllabus updated
- 2014/9/18
- Lecture notes updated
- 2014/10/14
- Access Index
-
- Semester
- Fall Semester
Outline of lecture
Prerequisite: VLSI design methodology or equivalent
Representation of Boolean function. Synthesis of two-level and multi-level combinational circuits. Synthesis of sequential circuits. Test and synthesis for test ability. Decomposition, allocation, assignment and scheduling in high-level synthesis.
Purpose of lecture
This course is designed to cover the underlining theories and technologies which support the systematic design process of current VLSIs.
Plan of lecture
1.Introduction - VLSI design methodology and computer-aided design (CAD) tools
2.Introduction - Hardware description language and hardware behavior model
3.Logic synthesis - Two-level logic minimization
4.Logic synthesis - Multi-level logic minimization
5.Logic synthesis - Area-optimal technology mapping
6.Logic synthesis - Delay-optimal technology mapping
7.Logic synthesis - Fan-out optimization
8.High-level synthesis - Design methodology
9.High-level synthesis - Operation scheduling
10.High-level synthesis - Resource allocation
11.Advanced topics in system-level design issues
Textbook and reference
Lecture notes can be downloaded from the WEB.
Recommended textbooks :
繝ｻSabih H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 1999
繝ｻSrinivas Devadas, et al., "Logic Synthesis", McGraw-Hill, 1994
繝ｻJan Vanhoof, et al., "High-Level Synthesis for Real-Time Digital
繝ｻSignal Processing", Kluwer Academic Publishers, 1992
Related and/or prerequisite courses
"Introduction to Algorithms"ｼ磯屬謨｣讒矩縺ｨ繧｢繝ｫ繧ｴ繝ｪ繧ｺ繝ｼ and "Integrated Circuit Design"ｼ磯寔遨榊屓霍ｯ險ｭ險茨ｼ are prerequisite.
Evaluation
Grades based on reports
Comments from lecturer
Students interested in any aspects of VLSI design are welcomed.
