- Lecturer
- Kunieda Hiroaki
- Place
- Wed3-4(S323)
- Credits
- Lecture2 Exercise0 Experiment0
- Code
- 56010
- Syllabus updated
- 2013/3/28
- Lecture notes updated
- 2013/3/21
- Semester
- Spring Semester
Outline of lecture
The design flow of Standard Cell Design for VLSI is discussed, which includes RTL design, Logic design, Logic verification, Layout design and Layout verification. In addition to that, FPGA design and System level Soc design will also be described.
Purpose of lecture
According to the design flow of Standard Cell Design, the hierarchical design and verification based on standard cell design will be discussed including hardware description language, logic design and layout design and their verifications.
Plan of lecture
ｼ托ｼ桟LSI Overview
ｼ抵ｼ桟lSI_Basic I
ｼ難ｼ桟lSI_Basic II
ｼ費ｼ惨tandard Cell Design_Overview
ｼ包ｼ惨tandard Cell Design_RTL
ｼ厄ｼ惨tandard Cell Design_Logic I
ｼ暦ｼ惨tandard Cell Design_LogicII
ｼ假ｼ惨tandard Cell Design_Verify
ｼ呻ｼ惨tandard Cell Design_Layout
10ｼ惨tandard Cell Design_Layout Verification
11ｼ薩PGA Design
12ｼ惨ystem on Chip (SoC) Design
Textbook and reference
Wayne Wolf: Modern VLSI Design (System on Silicon) Second Edition, Prentice Hall 1998.
Related and/or prerequisite courses
VLSI Layout Design, VLSI System Design are related subjects.
Evaluation
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Comments from lecturer
VLSI design is the basic knowledge for engineers of various fields. This lecture covers all aspects of VLSI design, especially for the beginners of VLSI design.
